Field of the Invention
The invention relates to a semiconductor memory, particularly a DRAM (Dynamic Random Access Memory), which has a plurality of similar memory banks which each include a quadratic matrix of memory cells. The invention also relates to an address loading method for such a semiconductor memory.
During read or write access to the DRAM, an address decoding unit uses a physical memory address to ascertain the memory bank and the addressed memory cell in this memory bank. Conventionally, during such an access, this involves transferring a read/write changeover signal, a “write-enable signal”, a row address activation signal, a “row address strobe” RAS, a column activation signal, and a “column address strobe” CAS to a DRAM controller. For access to the addressed memory cell, the RAS signal is first activated. The address decoding unit's row address buffers assigned to the individual memory banks then adopt the row address of the addressed memory cell. At the same time, a bank address decoder ascertains the memory bank in which the addressed memory cell/row is situated and activates the corresponding row address buffer with the stored row address. The selected row address buffer then drives the stored row address to an associated row decoder in the address decoding unit. This row decoder ascertains the addressed row in the memory cell array in the memory bank that responds via a corresponding word line WL.
Next, the CAS signal is activated and the DRAM controller writes the desired column address of the selected memory cell to the address decoding unit's column address buffers associated with the respective memory banks. The bank decoder in turn ascertains the memory bank containing the addressed memory cell/column and activates the corresponding memory address buffer with the stored column address. The selected memory address buffer then transfers the column address to the associated column address decoder, which ascertains the sought column within the memory cell array that responds via a corresponding bit line pair BL, −BL.
During a read access, the bit found is output by the addressed memory cell, is then amplified by a sense amplifier and is written to a data output buffer in the DRAM memory. For storage access, the DRAM controller additionally activates the WE signal. The information to be written is then transferred to a data input buffer, and is then forwarded to the addressed memory cell by a sense amplifier and is stored in the memory cell.
During the read or write access in a DRAM memory containing a plurality of memory banks, the row and column addresses for the selected memory cell are thus routed to all the memory banks and are stored in the corresponding row address and column address buffers in the address decoding unit. When the memory bank address decoded by the bank decoder has been applied, the selected row address or column address buffer then drives the row or column address on to the associated row-address or column address decoder, which decodes the selected row or column address. A drawback of this procedure is that, during the read or write operation, the row address and column address buffers of all the memory banks are always loaded with the respective address, even though a single memory bank is intended to be accessed. The consequence of this is that a large charging current is required, since all the signal lines and input gates in the corresponding row address and column address buffers need to be activated to store the row and column addresses.
Published U.S. patent application Ser. No. 20020054518 discloses a semiconductor memory in which the column address and the row address buses are combined into a common bus which is routed to the individual banks of the semiconductor memory. In this case, the address decoding unit has a demultiplexer connection upstream of the address decoder and the address buffer in order to be able to change over between the column address and the row address.